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DALLAS SEMICONDUCTOR
PRELIMINARY DS21Q50 Quad E1 Transceiver
PRELIMINARY FEATURES * 4 Complete E1 (CEPT) PCM-30/ISDN-PRI transceivers * Long and short haul line interfaces * 32-bit or 128-bit crystal-less jitter attenuator * Frames to FAS, CAS, CCS, and CRC4 formats * 4/8/16MHz clock synthesizer * Two-frame elastic store slip buffer on the receive side * Interleaving PCM Bus Operation up to 16.384MHz * 8-bit parallel control port that can be used directly on either multiplexed or non- multiplexed buses (Intel or Motorola) * Configurable for serial port operation * Detects and generates remote and AIS alarms * Fully independent transmit and receive functionality * Four separate loopback functions * PRBS generation/detection/error counting * Large counters for bipolar and code violations, CRC4 code word errors, FAS word errors, and E bits * Two user configurable outputs * 3.3V low power CMOS * 100-pin LQFP package (14mm X 14mm)
100 1
ORDERING INFORMATION (00 C to 700 C) (-400 C to +850 C)
DS21Q50L DS21Q50LN
DESCRIPTION The DS21Q50 E1 Quad Transceiver contains all of the necessary functions for connection to 4 E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to over 2km in length. The device can generate the necessary G.703 waveshapes for both 75 ohm coax and 120 ohm twisted pair cables. The onboard jitter attenuators (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framers locate the frame and multiframe boundaries and monitor the data streams for alarms. The device contains a set of internal registers, which the user can access, and control the operation of the unit via the parallel control port or serial port. The device fully meets all of the latest E1 specifications including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431, ETS 300 011, 300 233, and 300 166, as well as CTR12 and CTR4.
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TABLE OF CONTENTS 1. 2. 3.
DS21Q50
LIST OF FIGURES.........................................................................................................................4 LIST OF TABLES...........................................................................................................................5 INTRODUCTION ...........................................................................................................................6 3.1 3.2 FUNCTIONAL DESCRIPTION..........................................................................................................7 DOCUMENT REVISION HISTORY.........................................................................................8
4.
PIN DESCRIPTION......................................................................................................................10 4.1 PIN FUNCTION DESCRIPTION ............................................................................................15 4.1.1 System (Backplane) Interface Pins....................................................................................15 4.1.2 Alternate Jitter Attenuator ...............................................................................................16 4.1.3 Clock Synthesizer .............................................................................................................16 4.1.4 Parallel Port Control Pins................................................................................................17 4.1.5 Serial Port Control Pins...................................................................................................18 4.1.6 Line Interface Pins ...........................................................................................................19 4.1.7 Supply Pins ......................................................................................................................20
5.
HOST INTERFACE PORT ..........................................................................................................21 5.1 5.2 5.3 PARALLEL PORT OPERATION .....................................................................................................21 SERIAL PORT OPERATION ..........................................................................................................21 REGISTER MAP.....................................................................................................................24
6.
CONTROL, ID, AND TEST REGISTERS...................................................................................26 6.1 6.2 6.3 6.4 6.5 POWER-UP SEQUENCE ..............................................................................................................26 FRAMER LOOPBACK ..................................................................................................................30 AUTOMATIC ALARM GENERATION.............................................................................................31 REMOTE LOOPBACK ..................................................................................................................32 LOCAL LOOPBACK ....................................................................................................................32
7.
STATUS AND INFORMATION REGISTERS............................................................................35 7.1 CRC4 SYNC COUNTER..............................................................................................................37
8.
ERROR COUNT REGISTERS ....................................................................................................42 8.1 8.2 8.3 8.4 BPV OR CODE VIOLATION COUNTER.........................................................................................42 CRC4 ERROR COUNTER............................................................................................................43 E-BIT / PRBS BIT ERROR COUNTER .........................................................................................43 FAS ERROR COUNTER ..............................................................................................................44
9. 10. 11. 12. 13. 14.
DS0 MONITORING FUNCTION ................................................................................................45 PRBS GENERATION & DETECTION ...................................................................................48 SYSTEM CLOCK INTERFACE..............................................................................................49 TRANSMIT CLOCK SOURCE................................................................................................51 IDLE CODE INSERTION ........................................................................................................52 PER-CHANNEL LOOP BACK ................................................................................................53
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15. 16. 17. 18.
DS21Q50
ELASTIC STORE OPERATION .............................................................................................54 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................55 USER CONFIGURABLE OUTPUTS.......................................................................................58 LINE INTERFACE UNIT.........................................................................................................60
18.1 RECEIVE CLOCK AND DATA RECOVERY .....................................................................................60 18.1.1 Termination......................................................................................................................61 18.2 TRANSMIT WAVESHAPING AND LINE DRIVING ...........................................................................61 18.3 JITTER ATTENUATORS...............................................................................................................65 18.3.1 Clock And Data Jitter Attenuators....................................................................................65 18.3.2 Undedicated Clock Jitter Attenuator ................................................................................65 19. 20. 21. 21.1 21.2 22. 23. CMI (CODE MARK INVERSION)..........................................................................................67 INTERLEAVED PCM BUS OPERATION..............................................................................69 FUNCTIONAL TIMING DIAGRAMS ....................................................................................72 RECEIVE ...................................................................................................................................72 TRANSMIT ................................................................................................................................74 OPERATING PARAMETERS .................................................................................................78 AC TIMING PARAMETERS AND DIAGRAMS....................................................................79
23.1 MULTIPLEXED BUS AC CHARACTERISTICS.................................................................................79 23.2 NON-MULTIPLEXED BUS AC CHARACTERISTICS ........................................................................82 23.2.1 Serial Port........................................................................................................................85 23.3 RECEIVE AC CHARACTERISTICS ................................................................................................86 23.4 TRANSMIT AC CHARACTERISTICS .............................................................................................89 24. MECHANICAL DESCRIPTION..............................................................................................91
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DS21Q50
1. LIST OF FIGURES Figure 3-1 DS21Q50 SINGLE-CHIP TRANSCEIVER............................................................................. 9 Figure 5-1 SERIAL PORT OPERATION MODE 1.................................................................................22 Figure 5-2 SERIAL PORT OPERATION MODE 2.................................................................................22 Figure 5-3 SERIAL PORT OPERATION MODE 3.................................................................................22 Figure 5-4 SERIAL PORT OPERATION MODE 4.................................................................................23 Figure 18-1 EXTERNAL ANALOG CONNECTIONS (BASIC CONFIGURATION).............................62 Figure 18-2 EXTERNAL ANALOG CONNECTIONS (PROTECTED INTERFACE) ............................63 Figure 18-3 TRANSMIT WAVEFORM TEMPLATE ............................................................................64 Figure 18-4 JITTER TOLERANCE ........................................................................................................66 Figure 18-5 JITTER ATTENUATION....................................................................................................66 Figure 19-1 CMI CODING .....................................................................................................................67 Figure 19-2 EXAMPLE OF CMI CODE VIOLATION (CV) ..................................................................68 Figure 20-1 IBO CONFIGURATION USING 2 DS21Q50 QUAD TRANSCEIVERS (8 E1 Lines) .........71 Figure 21-1 RECEIVE FRAME AND MULTIFRAME TIMING ............................................................72 Figure 21-2 RECEIVE BOUNDARY TIMING (with elastic store disabled) ............................................72 Figure 21-3 RECEIVE BOUNDARY TIMING (with elastic store enabled) .............................................72 Figure 21-4 RECEIVE INTERLEAVE BUS OPERATION.....................................................................73 Figure 21-5 TRANSMIT FRAME AND MULTIFRAME TIMING .........................................................74 Figure 21-6 TRANSMIT BOUNDARY TIMING....................................................................................74 Figure 21-7 TRANSMIT INTERLEAVE BUS OPERATION..................................................................75 Figure 21-8 DS21Q50 FRAMER SYNCHRONIZATION FLOWCHART ...............................................76 Figure 21-9 DS21Q50 TRANSMIT DATA FLOW .................................................................................77 Figure 23-1 INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) ........................................................80 Figure 23-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1)...............................................................80 Figure 23-3 MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) .......................................................81 Figure 23-4 INTEL BUS READ TIMING (BTS=0 / MUX=0).................................................................83 Figure 23-5 INTEL BUS WRITE TIMING (BTS=0 / MUX=0)...............................................................83 Figure 23-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0) ......................................................84 Figure 23-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX=0) ....................................................84 Figure 23-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0).......................................................................85 Figure 23-9 RECEIVE AC TIMING (Receive elastic store disabled) .......................................................87 Figure 23-10 RECEIVE AC TIMING (Receive elastic store enabled)......................................................88 Figure 23-11 TRANSMIT AC TIMING (IBO Disabled) .........................................................................90 Figure 23-12 TRANSMIT AC TIMING (IBO Enabled) ..........................................................................90
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DS21Q50
2. LIST OF TABLES Table 4-1 PIN TABLE (By Function)......................................................................................................10 Table 4-2 PIN TABLE (By Pin Number).................................................................................................12 Table 5-1 BUS MODE SELECT .............................................................................................................21 Table 5-2 REGISTER MAP SORTED BY ADDRESS ............................................................................24 Table 6-1 SYNC/RESYNC CRITERIA...................................................................................................28 Table 7-1 ALARM CRITERIA ...............................................................................................................37 Table 10-1 TRANSMIT PRBS MODE SELECT.....................................................................................48 Table 10-2 RECEIVE PRBS MODE SELECT ........................................................................................48 Table 11-1 MASTER PORT SELECTION..............................................................................................50 Table 11-2 SYNTHESIZER OUTPUT SELECT .....................................................................................50 Table 17-1 OUTA AND OUTB FUNCTION SELECT............................................................................59 Table 18-1 LINE BUILD OUT SELECT IN LICR ..................................................................................61 Table 18-2 TRANSFORMER SPECIFICATIONS...................................................................................61 Table 20-1 IBO DEVICE ASSIGNMENT...............................................................................................70 Table 20-2 IBO SYSTEM CLOCK SELECT ..........................................................................................70
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DS21Q50
3. INTRODUCTION The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included for this type of application, Interleave Bus Option and a System Clock Synthesizer feature. The Interleave Bus Option allows up to 8 E1 data streams to be multiplexed onto a single high-speed PCM bus without additional external logic. The System Clock Synthesizer feature allows any of the E1 lines to be selected as the master source of clock for the system and for all the transmitters. This is also accomplished without the need of external logic. Each of the 4 transceivers has a clock and data jitter attenuator that can be assigned to either the transmit or receive path. In addition there is a single, undedicated clock jitter attenuator that can be hardware configured as the user needs. Each transceiver also contains a PRBS pattern generator and detector. Figure 20-1 shows a simplified typical application which terminates 8 E1 lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The 16.384MHz system clock is derived and phased locked to one of the 8 E1 lines. On the receive side of each port, an elastic store provides logical management of any slip conditions due to the asynchronous relationship of the 8 E1 lines. In this application all 8 transmitters are timed to the selected E1 line.
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DS21Q50
3.1 Functional Description The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS21Q50. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive framer where the digital serial stream is analyzed to locate the framing/multi-frame pattern. The DS21Q50 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of 0 dB to -43 dB which allows the device to operate on cables over 2km in length. The receive framer locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If needed, the receive elastic store can be enabled in order to absorb the phase and frequency differences between the recovered E1 data stream and an asynchronous backplane clock which is provided at the SYSCLK input. The clock applied at the SYSCLK input can be either a 2.048/4.096/8.192 or 16.384MHz clock. The transmit framer is independent from the receive in both the clock requirements and characteristics. The transmit formatter will provide the necessary frame/multiframe data overhead for E1 transmission. Reader' Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In s each 125 us frame, there are 32 eight-bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. The term "locked" is used to refer to two clock signals that are phase or frequency locked or derived from a common clock (i.e., a 8.192MHz clock may be locked to a 2.048MHz clock if they share the same 8KHz component). Throughout this data sheet, the following abbreviations will be used:
FAS CAS MF Si CRC4 CCS Sa E-bit TCLK RCLK
Frame Alignment Signal Channel Associated Signaling Multiframe International bits Cyclical Redundancy Check Common Channel Signaling Additional bits CRC4 Error Bits This generally refers to the transmit rate clock and may reference an actual input signal to the device (TCLK) or an internally derived signal used for transmission. This generally refers to the recovered network clock and may be a reference to an actual output signal from the device or an internal signal.
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DS21Q50
3.2 DOCUMENT REVISION HISTORY Date 3-4-99 4-12-99 5-11-99 7-19-99 9-28-99 2-1-00 Notes Initial release Add section on OUTA and OUTB pin functions. Add protected interface example. Add 75 / 120 ohm software selectable termination. CCR5.4 and section 18.1.1 Add Local Per-Channel Loop Back operation. CCR5.0 and section 14 Add PRBS information Add section on CMI Add Pinouts
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Figure 3-1 DS21Q50 SINGLE-CHIP TRANSCEIVER
MCLK
VCO / PLL User Outputs Select
DS21Q50
OUTA1 OUTB1
RECEIVE SIDE RRING1 RTIP1
DATA CLOCK SYNC Remote Loopback Receive Side Framer Elastic Store And IBO Buffer
RSER1 SYSCLK1 RSYNC1
TRANSMIT SIDE
Transmit Line I/F
Receive Line I/F Clock / Data Recovery Local Loopback
Jitter Attenuator Either transmit or receive path
Framer Loopback
Sync Control DATA CLOCK SYNC Transmit Side Formatter A BU Ck MUX B C IBO Buffer Divide by 2/4/8 Tx Ck MUX LOTC Detect A B
TSYNC1 TSER1
TRING1 TTIP1
TCLK1
TRANSCEIVER #1of 4
TRANSMIT CLOCK SOURCE
BackUp ClocK MUX Transceivers 2 ,3 and 4 RCLK Transceiver #2 RCLK Transceiver #3 RCLK Transceiver #4 MUX
SYSTEM CLOCK INTERFACE
2.048MHz
Parallel & Test Control Port (routed to all blocks)
Alternate Jitter Attenuator 4/8/16Mhz Synthesizer
REFCLK 4/8/16MCK
BTS0 BTS1 PBTS CS*
INT*
RD*(DS*) WR*(R/W*) TS0 TS1
A0 to A5 ALE(AS) / A6
D0 to D7 / AD0 to AD7
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AJACOI
AJACKI
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DS21Q50
4. PIN DESCRIPTION Table 4-1 PIN TABLE (By Function) PIN SIGNAL NAME, PARALLEL PORT ENABLED A0 A1 A2 A3 A4 ALE(AS)/A5 BTS0 BTS1 CS* D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 RD*(DS*) WR*(R/W*) INT* PBTS TS1 TS0 MCLK DVDD DVDD DVDD DVDD DVSS DVSS DVSS DVSS RVSS RVSS RVSS RVSS
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SIGNAL NAME, SERIAL PORT ENABLED
ICES OCES
TYPE
FUNCTION [Serial Port Mode In Brackets]
45 46 47 48 49 50 91 92 98 19 20 21 22 23 24 25 44 75 74 94 95 100 99 73 9 34 59 84 8 33 58 83 65 40 15 90
I I I I I I
SDO SCLK SDI
I I/O I/O I/O I/O I/O I/O I/O I/O I I O I I I I - - - - - - - - - - - -
Address Bus Bit 0 / Serial Port [Input Clock Edge Select] Address Bus Bit 1 / Serial Port [Output Clock Edge Select] Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Latch Enable /Address Bus Bit 5 Bus Type Select 0 Bus Type Select 1 Chip Select Data Bus Bit0/ Address/Data Bus Bit 0 Data Bus Bit1/ Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus Bit2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Data Bus Bit 7/Address/Data Bus Bit 7 [Serial Data Output] Read Input(Data Strobe) [Serial Port Clock] Write Input(Read/Write) [Serial Data Input] Interrupt Parallel Bus Type Select Transceiver Select 1 Transceiver Select 0 Master Clock Input Digital Positive Supply Digital Positive Supply Digital Positive Supply Digital Positive Supply Digital Signal Ground Digital Signal Ground Digital Signal Ground Digital Signal Ground Receive Analog Signal Ground Receive Analog Signal Ground Receive Analog Signal Ground Receive Analog Signal Ground 020200
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68 43 18 93 77 52 27 2 78 53 28 3 71 72 67 42 17 92 63 38 13 88 64 39 14 89 66 41 16 91 62 37 12 87 80 55 30 5 79 54 29 4 81 56 31 6 82 57 32 7 RVDD RVDD RVDD RVDD TVSS TVSS TVSS TVSS TVDD TVDD TVDD TVDD 4/8/16MCK REFCLK RRING1 RRING2 RRING3 RRING4 RSER1 RSER2 RSER3 RSER4 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RTIP1 RTIP2 RTIP3 RTIP4 SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 TCLK1 TCLK2 TCLK3 TCLK4 TRING1 TRING2 TRING3 TRING4 TSER1 TSER2 TSER3 TSER4 TSYNC1 TSYNC2 TSYNC3 TSYNC4 - - - - - - - - - - - - O I/O I I I I O O O O I/O I/O I/O I/O I I I I I I I I I I I I O O O O I I I I I/O I/O I/O I/O
DS21Q50
Receive Analog Positive Supply Receive Analog Positive Supply Receive Analog Positive Supply Receive Analog Positive Supply Transmit Analog Signal Ground Transmit Analog Signal Ground Transmit Analog Signal Ground Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Positive Supply Transmit Analog Positive Supply Transmit Analog Positive Supply 4.096, 8.192 or 16.384 MHz Clock Reference Clock Receive Analog Ring Input Receive Analog Ring Input Receive Analog Ring Input Receive Analog Ring Input Receive Serial Data Receive Serial Data Receive Serial Data Receive Serial Data Receive Sync Receive Sync Receive Sync Receive Sync Receive Analog Tip Input Receive Analog Tip Input Receive Analog Tip Input Receive Analog Tip Input Transmit/Receive System Clock Transmit/Receive System Clock Transmit/Receive System Clock Transmit/Receive System Clock Transmit Clock Transmit Clock Transmit Clock Transmit Clock Transmit Analog Ring Output Transmit Analog Ring Output Transmit Analog Ring Output Transmit Analog Ring Output Transmit Serial Data Transmit Serial Data Transmit Serial Data Transmit Serial Data Transmit Sync Transmit Sync Transmit Sync Transmit Sync
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76 51 26 1 61 36 11 86 60 35 10 85 70 69 TTIP1 TTIP2 TTIP3 TTIP4 OUTA1 OUTA2 OUTA3 OUTA4 OUTB1 OUTB2 OUTB3 OUTB4 AJACKI AJACKO O O O O O O O O O O O O I O
DS21Q50
Transmit Analog Tip Output Transmit Analog Tip Output Transmit Analog Tip Output Transmit Analog Tip Output User Selectable Output A User Selectable Output A User Selectable Output A User Selectable Output A User Selectable Output B User Selectable Output B User Selectable Output B User Selectable Output B Alternate Jitter Attenuator Clock Input Alternate Jitter Attenuator Clock Output
Table 4-2 PIN TABLE (By Pin Number) PIN SIGNAL NAME, PARALLEL PORT ENABLED TTIP4 TVSS TVDD TRING4 TCLK4 TSER4 TSYNC4 DVSS DVDD OUTB3 OUTA3 SYSCLK3 RSER3 RSYNC3 RVSS RTIP3 RRING3 RVDD D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 TTIP3 SIGNAL NAME, SERIAL PORT ENABLED TYPE FUNCTION [Serial Port Mode In Brackets] O - - O I I I/O - - O O I O I/O - I I - I/O I/O I/O I/O I/O I/O I/O O Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Data Bus Bit0/ Address/Data Bus Bit 0 Data Bus Bit1/ Address/Data Bus Bit 1 Data Bus Bit 2/Address/Data Bus Bit2 Data Bus Bit 3/Address/Data Bus Bit 3 Data Bus Bit4/Address/Data Bus Bit 4 Data Bus Bit 5/Address/Data Bus Bit 5 Data Bus Bit 6/Address/Data Bus Bit 6 Transmit Analog Tip Output
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
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27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 TVSS TVDD TRING3 TCLK3 TSER3 TSYNC3 DVSS DVDD OUTB2 OUTA2 SYSCLK2 RSER2 RSYNC2 RVSS RTIP2 RRING2 RVDD D7/AD7 A0 A1 A2 A3 A4 ALE(AS)/A5 TTIP2 TVSS TVDD TRING2 TCLK2 TSER2 TSYNC2 DVSS DVDD OUTB1 OUTA1 SYSCLK1 RSER1 RSYNC1 RVSS RTIP1 RRING1 RVDD AJACKO AJACKI 4/8/16MCK REFCLK MCLK - - O I I I/O - - O O I O I/O - I I - I/O I I I I I I O - - O I I I/O - - O O I O I/O - I I - O I O I/O I
DS21Q50
Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Data Bus Bit 7/Address/Data Bus Bit 7 [Serial Data Output] Address Bus Bit 0 / Serial Port [Input Clock Edge Select] Address Bus Bit 1 / Serial Port [Output Clock Edge Select] Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Latch Enable /Address Bus Bit 5 Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Alternate Jitter Attenuator Clock Output Alternate Jitter Attenuator Clock Input 4.096, 8.192 or 16.384 MHz Clock Reference Clock Master Clock Input
SDO
ICES OCES
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74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 WR*(R/W*) RD*(DS*) TTIP1 TVSS TVDD TRING1 TCLK1 TSER1 TSYNC1 DVSS DVDD OUTB4 OUTA4 SYSCLK4 RSER4 RSYNC4 RVSS RTIP4 RRING4 RVDD INT* PBTS BTS0 BTS1 CS* TS0 TS1 SDI SCLK I I O - - O I I I/O - - O O I O I/O - I I - O I
DS21Q50
Write Input(Read/Write) [Serial Data Input] Read Input(Data Strobe) [Serial Port Clock] Transmit Analog Tip Output Transmit Analog Signal Ground Transmit Analog Positive Supply Transmit Analog Ring Output Transmit Clock Transmit Serial Data Transmit Sync Digital Signal Ground Digital Positive Supply User Selectable Output B User Selectable Output A Transmit/Receive System Clock Receive Serial Data Receive Sync Receive Analog Signal Ground Receive Analog Tip Input Receive Analog Ring Input Receive Analog Positive Supply Interrupt Parallel Bus Type Select Bus Type Select 0 Bus Type Select 1 Chip Select Transceiver Select 0 Transceiver Select 1
I I I
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DS21Q50
4.1 PIN FUNCTION DESCRIPTION
4.1.1 System (Backplane) Interface Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048 MHz primary clock. Used to clock data through the transmit formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when IBO disabled. Sampled on the falling edge of SYSCLK when the IBO function is enabled. Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input / Output As an input, pulse at this pin will establish either frame or multiframe boundaries for the transmitter. As an output, can be programmed to output either a frame or multiframe pulse. Signal Name: RSER Signal Description: Receive Serial Data Signal Type: Output Received NRZ serial data. Updated on rising edges of RCLK when the receive elastic store is disabled. Updated on the rising edges of SYSCLK when the receive elastic store is enabled. Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC4 multiframe boundaries. If the receive elastic store is enabled, then this pin can be enabled to be an input at which a frame boundary pulse synchronous with SYSCLK is applied. Signal Name: SYSCLK Signal Description: System Clock Signal Type: Input 2.048MHz clock that is used to clock data out of the receive elastic store. When the Interleave Bus Option is enable this can be a 4.096MHz, 8.192MHz or 16.384MHz clock Signal Name: OUTA Signal Description: User Selectable Output A Signal Type: Output A multifunction pin that can be programmed by the host to output various alarms, clocks or data, or used to control external circuitry.
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DS21Q50
Signal Name: OUTB Signal Description: User Selectable Output B Signal Type: Output A multifunction pin that can be programmed by the host to output various alarms, clocks or data, or used to control external circuitry.
4.1.2 Alternate Jitter Attenuator Signal Name: AJACKI Signal Description: Alternate Jitter Attenuator Clock Input Signal Type: Input Clock input to alternate jitter attenuator Signal Name: AJACKO Signal Description: Alternate Jitter Attenuator Clock Output Signal Type: Output Clock output of alternate jitter attenuator
4.1.3 Clock Synthesizer Signal Name: 4/8/16MCK Signal Description: 4.096MHz / 8.192MHz / 16.384MHz Clock Output Signal Type: Output A 4.096MHz, 8.192MHz, or 16.384MHz clock output that is referenced to one of the 4 recovered line clocks (RCLKs) or to an external 2.048MHz reference. Signal Name: REFCLK Signal Description: Reference Clock Signal Type: Input/Output Can be configured as an output to source a 2.048MHz reference clock or as an input to supply a 2.048MHz reference clock from an external source to the clock synthesizer.
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DS21Q50
4.1.4 Parallel Port Control Pins Signal Name: INT* Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Active low, open drain output Signal Name: BTS0 Signal Description: Bus Type Select Bit 0 Signal Type: Input Used in conjunction with BTS1 to select between MUX, NON-MUX, serial bus operation and output High Z mode. Signal Name: BTS1 Signal Description: Bus Type Select Bit 0 Signal Type: Input Used in conjunction with BTS0 to select between MUX, NON-MUX, serial bus operation and output High Z mode. Signal Name: TS0 Signal Description: Transceiver Select Bit 0 Signal Type: Input Used in conjunction with FS1 to select one of four Transceivers Signal Name: TS1 Signal Description: Transceiver Select Bit 0 Signal Type: Input Used in conjunction with FS0 to select one of four Transceivers Signal Name: PBTS Signal Description: Parallel Bus Type Select Signal Type: Input Used to select between Motorola and Intel parallel bus types. Signal Name: Signal Description: AD0 TO AD7/SDO Data Bus or Address/Data Bus[D0 to D6] Data Bus or Address/Data bus[D7] / Serial Port Output Signal Type: Input/Output In non-multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as a 8-bit multiplexed address / data bus. Signal Name: A0 TO A5 Signal Description: Address Bus Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
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DS21Q50
Signal Name: RD*(DS*)/SCLK Signal Description: Read Input - Data Strobe / Serial Port Clock Signal Type: Input RD* and DS* are active low signals. DS active HIGH when MUX = 0. See bus timing diagrams. Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS* is an active low signal. Signal Name: ALE(AS)/A6 Signal Description: Address Latch Enable(Address Strobe) or A6 Signal Type: Input In non-multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to de-multiplex the bus on a positive-going edge. Signal Name: WR*(R/W*)/SDI Signal Description: Write Input(Read/Write) / Serial Port Data Input Signal Type: Input WR* is an active low signal.
4.1.5 Serial Port Control Pins Signal Name: SDO Signal Description: Serial Port Output Signal Type: Output Data at this output can be updated on the rising or falling edge of SCLK Signal Name: SDI Signal Description: Serial Port Data Input Signal Type: Input Data at this input can be sampled on the rising or falling edge of SCLK Signal Name: ICES Signal Description: Input Clock Edge Select Signal Type: Input Used to select which SCLK clock edge will sample data at SDI Signal Name: OCES Signal Description: Output Clock Edge Select Signal Type: Input Used to select which SCLK clock edge will update data at SDO Signal Name: SCLK Signal Description: Serial Port Clock Signal Type: Input Used to clock data into and out of the serial port
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DS21Q50
4.1.6 Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048 MHz (? ? 50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. Signal Name: RTIP & RRING Signal Description: Receive Tip and Ring Signal Type: Input Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the E1 line. See Section 18 for details. Signal Name: TTIP & TRING Signal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect via a 1:2 step-up transformer to the E1 line. See Section 18 for details.
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DS21Q50
4.1.7 Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3 volts +/-5% Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3 volts +/-5% Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 3.3 volts +/-5% Should be tied to the RVDD and DVDD pins. Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply 0.0 volts. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0.0 volts. Should be tied to DVSS and TVSS. Signal Name: TVSS Signal Description: Transmit Analog Signal Ground Signal Type: Supply 0.0 volts. Should be tied to DVSS and RVSS.
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DS21Q50
5. HOST INTERFACE PORT The DS21Q50 is controlled via either a non-multiplexed bus, a multiplexed bus or serial interface bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Table 5-1 for a description of the bus configurations. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics in Section 20 for more details. Table 5-1 BUS MODE SELECT PBTS 0 0 1 1 X X BTS1 0 0 0 0 1 1 BTS0 0 1 0 1 0 1 Parallel Port Mode Intel Multiplexed Intel Non-Multiplexed Motorola Multiplexed Motorola Non-Multiplexed Serial TEST (Outputs High Z)
5.1 Parallel Port Operation When using the parallel interface on the DS21Q50 (BTS1 = 0) the user has the option for either multiplexed bus operation (BTS1 = 0, BTS0 = 0) or non-multiplexed bus operation (BTS1 = 0, BTS0 = 1). The DS21Q50 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in section 23 for more details. 5.2 Serial Port Operation Setting BTS1 pin = 1 and the BTS0 pin = 0 enables the serial bus interface on the DS21Q50. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 23 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 5-1, Figure 5-2, Figure 5-3, and Figure 5-4 for more details. Reading or writing to the internal registers requires writing one address/command byte prior to transferring register data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write (0). The next 5 bits identify the register address. The next bit is reserved and must be set to 0 for proper operation. The last bit (MSB) of the address/command byte enables the burst mode when set to 1. The burst mode causes all registers to be consecutively written or read. All data transfers are initiated by driving the CS* input low. When Input Clock-Edge Select (ICES) is low, input data is latched on the rising edge of SCLK and when ICES is high, input data is latched on the falling edge of SCLK. When Output Clock-Edge Select (OCES) is low, data is output on the falling edge of SCLK and when OCES is high, data is output on the rising edge of SCLK. Data is held until the next falling or rising edge. All data transfers are terminated if the CS* input transitions high. Port control logic is disabled and SDO is tri-stated when CS* is high.
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DS21Q50
Figure 5-1 SERIAL PORT OPERATION MODE 1
ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK)
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CS*
SDI R/W* (lsb) SDO A1 A2 A3 A4 A5 0 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
Figure 5-2 SERIAL PORT OPERATION MODE 2
ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 0 (update SDO on falling edge of SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS*
SDI R/W* (lsb) SDO A1 A2 A3 A4 A5 0 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
Figure 5-3 SERIAL PORT OPERATION MODE 3
ICES = 0 (sample SDI on the rising edge of SCLK) OCES = 0 (update SDO on falling edge of SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS*
SDI R/W* (lsb) SDO A1 A2 A3 A4 A5 0 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
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DS21Q50
Figure 5-4 SERIAL PORT OPERATION MODE 4
ICES = 0 (sample SDI on the rising edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CS*
SDI R/W* (lsb) SDO A1 A2 A3 A4 A5 0 B (msb) D0 (lsb) D1 D2 D3 D4 D5 D6 D7 (msb)
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DS21Q50
5.3 REGISTER MAP Table 5-2 REGISTER MAP SORTED BY ADDRESS ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 R/W R R R R R R R R R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R REGISTER NAME BPV or Code Violation Count 1 BPV or Code Violation Count 2 CRC4 Error Count 1 CRC4 Error Count 2 E-Bit Count 1 / PRBS Error Count 1 E-Bit Count 2 / PRBS Error Count 2 FAS Error Count 1 FAS Error Count 2 Receive Information Synchronizer Status Status 1 Status 2 Unused Unused Unused Device ID SEE NOTE 2 Receive Control Transmit Control 1 Common Control 1 Common Control 2 Common Control 3 Common Control 4 Common Control 5 Line Interface Control Register Interrupt Mask 1 Interrupt Mask 2 Output A Control Output B Control Interleave Bus Operation Register System Clock Interface Control Register SEE NOTE 2 Test 2 SEE NOTE 1 Test 3 SEE NOTE 1 Transmit Align Frame Transmit Non-Align Frame Transmit DS0 Monitor Transmit Idle Definition Transmit Idle 1 Transmit Idle 2 Transmit Idle 3 Transmit Idle 4 Receive Align Frame Receive Non-Align Frame REGISTER ABBREVIATION VCR1 VCR2 CRCCR1 CRCCR2 EBCR1 EBCR2 FASCR1 FASCR2 RIR SSR SR1 SR2 IDR RCR TCR CCR1 CCR2 CCR3 CCR4 CCR5 LICR IMR1 IMR2 OUTAC OUTBC IBOR SCICR TEST2 (set to 00h) TEST3 (set to 00h) TAF TNAF TDS0M TIDR TIR1 TIR2 TIR3 TIR4 RAF RNAF
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2A 2B 2C 2D 2E 2F R R/W R/W R/W R/W R/W Receive DS0 Monitor Per-Channel Loopback Control 1 Per-Channel Loopback Control 2 Per-Channel Loopback Control 3 Per-Channel Loopback Control 4 Test 1 SEE NOTE 1
DS21Q50
RDS0M PCLB1 PCLB2 PCLB3 PCLB4 TEST1 (set to 00h)
NOTES: 1. Test Registers are used only by the factory; these registers must be cleared (set to all zeros) on power- up initialization to insure proper operation. 2 The Device ID register and the System Clock Interface Control register exist in Transceiver #1 only. (TS0, TS1 = 0)
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DS21Q50
6. CONTROL, ID, AND TEST REGISTERS
The operation of the DS21Q50 is configured via a set of seven control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There is one Receive Control Register (RCR), one Transmit Control Registers (TCR), and five Common Control Registers (CCR1 to CCR5). Each of these registers are described in this section. There is a device Identification Register (IDR) at address 0Fh. The MSB of this read-only register is fixed to a one indicating that an E1 Quad Transceiver is present. The next 3 MSBs are reserved for future use. The lower 4 bits of the device ID register are used to identify the revision of the device. This register exists in Transceiver #1 only. (TS0, TS1 = 0) The Test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On power-up, the Test registers should be set to 00h in order for the DS21Q50 to operate properly. IDR (0F Hex): DEVICE IDENTIFICATION REGISTER SYMBOL 1 ID3 ID2 ID1 ID0 BIT 7 6 5 4 3 1 2 0 NAME AND DESCRIPTION Bit 7. Bit 6. Bit 5. Bit 4. Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. Chip Revision Bit 1. Chip Revision Bit 0. LSB of a decimal code that represents the chip revision.
6.1 Power-Up Sequence On power-up, after the supplies are stable the DS21Q50 should be configured for operation by writing to all of the internal registers (this includes setting the Test Registers to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from zero to one to reset the line interface circuitry (it will take the device about 40ms to recover from the LIRST bit being toggled). Finally, after the SYSCLK input is stable, the ESR bits (CCR4.5 & CCR4.6) should be toggled from a zero to a one (this step can be skipped if the elastic store is disabled).
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DS21Q50
RCR (10 Hex): RECEIVE CONTROL REGISTER SYMBOL RSMF BI T 7 NAME AND DESCRIPTION RSYNC Multiframe Function. Only used if the RSYNC pin is programmed in the multiframe mode (RCR.6=1). 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries RSYNC Mode Select. 0 = frame mode (see the timing in Section 21.1) 1 = multiframe mode (see the timing in Section 21.1) RSYNC I/O Select. (Note: this bit must be set to zero when RCR .4=0). 0 = RSYNC is an output (depends on RCR.6) 1 = RSYNC is an input (only valid if elastic store enabled) Receive Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Unused. Should Be set = 0 for proper operation Frame Resync Criteria. 0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Sync Enable. 0 = auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resync is initiated. Must be cleared and set again for a subsequent resync.
RSM
6
RSIO
5
RESE
4
FRC
3 2
SYNCE
1
RESYNC
0
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DS21Q50
Table 6-1 SYNC/RESYNC CRITERIA FRAME OR MULTIFRAME LEVEL FAS SYNC CRITERIA RESYNC CRITERIA ITU SPEC.
FAS present in frame N and N + 2, and FAS not present in frame N + 1
Three consecutive incorrect FAS received Alternate (RCR1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non-FAS received 915 or more CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error
G.706 4.1.1 4.1.2
CRC4 CAS
Two valid MF alignment words found within 8 ms Valid MF alignment word found and previous timeslot 16 contains code other than all zeros
G.706 4.2 and 4.3.2 G.732 5.2
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DS21Q50
TCR(11 Hex): TRANSMIT CONTROL REGISTER SYMBOL BI T 7 NAME AND DESCRIPTION
IFSS
TFPT
6
AEBE
5
TUA1
4
TSiS
3
TSA1
2
TSM
1
TSIO
0
Internal Frame Sync Select. 0 = TSYSC normal 1 = If TSYNC is in the INPUT mode (TSIO = 0) then TSYNC is internally replaced by the recovered receive frame sync. The TSYNC pin is ignored 1 = If TSYNC is in the OUTPUT mode (TSIO = 1) then TSYNC outputs the recovered multiframe frame sync. Transmit Timeslot 0 Pass Through. 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Automatic E-Bit Enable. 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Transmit Unframed All Ones. 0 = transmit data normally 1 = transmit an unframed all one' code s Transmit International Bit Select. 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR.6 must be set to 0) Transmit Signaling All Ones. 0 = normal operation 1 = force timeslot 16 in every frame to all ones TSYNC Mode Select. 0 = frame mode (see the timing in Section 21.2) 1 = CAS and CRC4 multiframe mode (see the timing in Section 21.2) TSYNC I/O Select. 0 = TSYNC is an input 1 = TSYNC is an output
NOTE: See Figure 21-9 for more details about how the Transmit Control Register affects the operation of the DS21Q50.
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DS21Q50
CCR1 (12 Hex): COMMON CONTROL REGISTER 1 SYMBOL BI T 7 NAME AND DESCRIPTION
FLB
THDB3
6
TIBE TCRC4
5 4
RSMS
3
RHDB3
2
PCLMS
1
RCRC4
0
Framer Loopback. See Section 6.2 for details 0=loopback disabled 1=loopback enabled Transmit HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Transmit Insert Bit Error. A zero to one transition causes a single bit error to be inserted in the transmit path Transmit CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled Receive Signaling Mode Select. 0=CAS signaling mode. Receiver will search for the CAS MF alignment signal 1=CCS signaling mode. Receiver will not search for the CAS MF alignment signal Receive HDB3 Enable. 0=HDB3 disabled 1=HDB3 enabled Per Channel Loopback Mode Select. See Section 14 for details 0 = Remote Per Channel Loopback 1 = Local Per Channel Loopback Receive CRC4 Enable. 0=CRC4 disabled 1=CRC4 enabled
6.2 Framer Loopback When CCR1.7 is set to a one, the DS21Q50 will enter a Framer LoopBack (FLB) mode. See Figure 3-1for more details. This loopback is useful in testing and debugging applications. In FLB, the SCT will loop data from the transmitter back to the receiver. When FLB is enabled, the following will occur:
1. Data will be transmitted as normal at TPOSO and TNEGO. 2. Data input via RPOSI and RNEGI will be ignored. 3. The RCLK output will be replaced with the TCLK input.
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CCR2 (13 Hex): COMMON CONTROL REGISTER 2 SYMBOL ECUS BIT 7 NAME AND DESCRIPTION
DS21Q50
VCRFS
6
AAIS
5
ARA
4
RSERC
3
LOTCMC
2
RCLA
1
TCLKSRC
0
Error Counter Update Select. See Section 8 for details. 0=update error counters once a second 1=update error counters every 62.5 ms (500 frames) VCR Function Select. See Section 8 for details. 0=count BiPolar Violations (BPVs) 1=count Code Violations (CVs) Automatic AIS Generation. 0=disabled 1=enabled Automatic Remote Alarm Generation. 0=disabled 1=enabled RSER Control. 0=allow RSER to output data as received under all conditions 1=force RSER to one under loss of frame alignment conditions Loss of Transmit Clock Mux Control. Determines whether the transmit formatter should switch to the ever present RCLK if the TCLK should fail to transition (see Figure 3-1). 0=do not switch to RCLK if TCLK stops 1=switch to RCLK if TCLK stops Receive Carrier Loss (RCL) Alternate Criteria. 0=RCL declared upon 255 consecutive zeros (125 us) 1=RCL declared upon 2048 consecutive zeros (1 ms) Transmit Clock Source Select. This function allows the user to internally select RCLK as the clock source for the transmit formatter. 0 = Source of transmit clock determined by CCR2.2 (LOTCMC) 1 = Force transmitter to internally switch to RCLK as source of transmit clock. Signal at TCLK pin is ignored
6.3 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one' reception, or s) loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer will either force an AIS alarm. When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all one' s) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will either transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant Remote Alarm will be transmitted if the DS21Q50 cannot find CRC4 multiframe synchronization within 400 ms as per G.706.
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DS21Q50
CCR3 (14 Hex): COMMON CONTROL REGISTER 3 SYMBOL RLB BIT 7 NAME AND DESCRIPTION Remote Loopback. See Section 6.4 for details 0 = loopback disabled 1 = loopback enabled Local Loopback. See Section 6.5 for details 0=loopback disabled 1=loopback enabled Line Interface AIS Generation Enable. 0=allow normal data to be transmitted at TTIP and TRING 1=force unframed all ones to be transmitted at TTIP and TRING at the MCLK rate Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 9 or details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
LLB
6
LIAIS
5
TCM4
4
TCM3 TCM2 TCM1 TCM0
3 2 1 0
6.4 Remote Loopback When CCR4.7 is set to a one, the DS21Q50 will be forced into Remote LoopBack (RLB). In this loopback, data input via the RPOSI and RNEGI pins will be transmitted back to the TPOSO and TNEGO pins. Data will continue to pass through the receive framer of the DS21Q50 as it would normally and the data from the transmit formatter will be ignored. Please see Figure 3-1 for more details.
6.5 Local Loopback When CCR4.6 is set to a one, the DS21Q50 will be forced into Local LoopBack (LLB). In this loopback, data will continue to be transmitted as normal. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. Please see Figure 3-1 for more details.
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DS21Q50
CCR4 (15 Hex): COMMON CONTROL REGISTER 4 SYMBOL LIRST BIT 7 NAME AND DESCRIPTION Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Receive Elastic Store Align. Setting this bit from a zero to a one may force the receive elastic store' write/read pointers to a minim separation of half a frame. s No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less then half a frame, the command will be executed and data will be disrupted. Should be toggled after SYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. See Section 15 for details. Receive Elastic Store Reset. Setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. Receive data is lost during the reset. Should be toggled after SYSCLK has been applied and is stable. Must be cleared and set again for a subsequent reset. See Section 15 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 9 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
RESALGN
6
RESR
5
RCM4
4
RCM3 RCM2 RCM1 RCM0
3 2 1 0
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CCR5 (16 Hex): COMMON CONTROL REGISTER 5 SYMBOL LIUODO BIT 7 NAME AND DESCRIPTION
DS21Q50
CDIG
6
LIUSI
5
IRTSEL
4
TPRBS1 TPRBS0 RPRBS1 RPRBS0
3 2 1 0
Line Interface Open Drain Option. This control bit determines whether the TTIP and TRING outputs will be open drain or not. The line driver outputs can be forced open drain to allow 6Vpeak pulses to be generated or to allow the creation of a very low power interface. 0 = allow TTIP and TRING to operate normally 1 = force the TTIP and TRING outputs to be open drain Customer Disconnect Indication Generator. This control bit determines whether the Line Interface will generate an unframed ...1010... pattern at TTIP and TRING instead of the normal data pattern. 0 = generate normal data at TTIP & TRING 1 = generate a ...1010... pattern at TTIP and TRING Line Interface G.703 Synchronization Interface Enable. This control bit determines whether the line receiver should handle a normal E1 signal (Section 6 of G.703) or a 2.048MHz synchronization signal (Section 10 of G.703). This control has no affect on the line interface transmitter. 0 = line receiver configured to support a normal E1 signal 1 = line receiver configured to support a synchronization signal Receive Termination Select. This function applies internal parallel resistance to the normal 120 ohm external termination to create a 75 ohm termination. 0 = normal 120 ohm external termination 1 = internally adjust receive termination to 75 ohms Transmit PRBS Mode Bit 1. See Table 10-1 Transmit PRBS Mode bit 0. See Table 10-1 Receive PRBS Mode bit 1. See Table 10-2 Receive PRBS Mode bit 0. See Table 10-2
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DS21Q50
7. STATUS AND INFORMATION REGISTERS There is a set of four registers that contain information on the current real time status of a framer in the DS21Q50, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), and Synchronizer status Register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The Synchronizer Status Register contents are not latched. This means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still present). The user will always proceed a read of the SR1, SR2 and RIR registers with a write. The byte written to the register will inform the framer which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is written to a bit location, the read register will be updated with the latest information. When a zero is written to a bit position, the read register will not be updated and the previous value will be held. A write to the status and information registers will be immediately followed by a read of the same register. The read result should be logically AND' with the mask byte that was just written and this value should be written back into ed the same register to insure that bit does indeed clear. This second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. This write-read- write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21Q50 with higher-order software languages. The SSR register operates differently than the other three. It is a read only register and it reports the status of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of this register with a write. The SR1and SR2 registers have the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the alarms and events in SR1and SR2 can be either masked or unmasked from the interrupt pin via Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2). The interrupts caused by alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently than the interrupts caused by events in SR1 and SR2 (namely RSA1, RDMA, RSA0, RSLIP, RMF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). The alarm caused interrupts will force the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in Table 7-1). The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur even if the alarm is still present. The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
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DS21Q50
RIR (08 Hex): RECEIVE INFORMATION REGISTER SYMBOL RGM1 RGM0 JALT RESF RESE CRCRC FASRC CASRC BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION Receive Gain Monitor Bit 1. Receive Gain Monitor Bit 0. Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches to within 4-bits of its limit; useful for debugging jitter attenuation operation. Receive Elastic Store Full. Set when the receive elastic store buffer fills and a frame is deleted. Receive Elastic Store Empty. Set when the receive elastic store buffer empties and a frame is repeated. CRC Resync Criteria Met. Set when 915/1000 code words are received in error. FAS Resync Criteria Met. Set when 3 consecutive FAS words are received in error. CAS Resync Criteria Met. Set when 2 consecutive CAS MF alignment words are received in error.
SSR (09 Hex): SYNCHRONIZER STATUS REGISTER SYMBOL CSC5 CSC4 CSC3 CSC2 CSC0 FASSA CASSA CRC4SA BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CRC4 Sync Counter Bit 4. CRC4 Sync Counter Bit 3. CRC4 Sync Counter Bit 2. CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter Bit 1 is not accessible. FAS Sync Active. Set while the synchronizer is searching for alignment at the FAS level. CAS MF Sync Active. Set while the synchronizer is searching for the CAS MF alignment word. CRC4 MF Sync Active. Set while the synchronizer is searching for the CRC4 MF alignment word.
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DS21Q50
7.1 CRC4 Sync Counter The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover.
Table 7-1 ALARM CRITERIA ALARM RSA1 (receive signaling all ones) RSA0 (receive signaling all zeros) RDMA (receive distant multiframe alarm) RUA1 (receive unframed all ones) RRA (receive remote alarm) RCL (receive carrier loss) SET CRITERIA over 16 consecutive frames (one full MF) timeslot 16 contains less than three zeros over 16 consecutive frames (one full MF) timeslot 16 contains all zeros bit 6 in timeslot 16 of frame 0 set to one for two consecutive MF less than three zeros in two frames (512-bits) bit 3 of non-align frame set to one for three consecutive occasions 255 (or 2048) consecutive zeros received CLEAR CRITERIA over 16 consecutive frames (one full MF) timeslot 16 contains three or more zeros over 16 consecutive frames (one full MF) timeslot 16 contains at least a single one bit 6 in timeslot 16 of frame 0 set to zero for two consecutive MF more than two zeros in two frames (512-bits) bit 3 of non-align frame set to zero for three consecutive occasions in 255-bit times, at least 32 ones are received ITU SPEC. G.732 4.2 G.732 5.2 O.162 2.1.5 O.162 1.6.1.2 O.162 2.1.4 G.775 / G.962
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DS21Q50
SR1 (0A Hex): STATUS REGISTER 1 SYMBOL RSA1 BIT 7 NAME AND DESCRIPTION Receive Signaling All Ones. Set when the contents of timeslot 16 contains less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Both RSA1 and RSA0 will be set if a change in signaling is detected. Receive Distant MF Alarm. Set when bit-6 of timeslot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. Receive Signaling All Zeros. Set when over a full MF, timeslot 16 contains all zeros. Both RSA1 and RSA0 will be set if a change in signaling is detected. Receive Elastic Store Slip. Set when the elastic store has either repeated or deleted a frame of data. Receive Unframed All Ones. Set when an unframed all ones code is received at RPOSI and RNEGI. Receive Remote Alarm. Set when a remote alarm is received at RPOSI and RNEGI. Receive Carrier Loss. Set when 255 (or 2048 if CCR2.1=1) consecutive zeros have been detected at RTIP and RRING. (note: a receiver carrier loss based on data received at RPOSI and RNEGI is available in the HSR register) Receive Loss of Sync. Set when the device is not synchronized to the receive E1 stream.
RDMA
6
RSA0 RSLIP RUA1 RRA RCL
5 4 3 2 1
RLOS
0
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SR2 (0B Hex): STATUS REGISTER 2 SYMBOL RMF RAF TMF SEC TAF LOTC RCMF PRBSD BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION Receive CAS Multiframe. Set every 2 ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Receive Align Frame. Set every 250 ms at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Transmit Multiframe. Set every 2 ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. One Second Timer. Set on increments of one second based on RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms instead of once a second. Transmit Align Frame. Set every 250 ? s at the beginning of align frames. Used to alert the host that the TAF and TNAF registers need to be updated. Loss of Transmit Clock. Set when the TCLK pin has not transitioned for one channel time (or 3.9 ms). Will force the LOTC pin high if enabled via TCR2.0. Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if CRC4 is disabled. Pseudo Random Bit Sequence Detect. When receive PRBS is enabled this bit will be set when the 215-1 PRBS pattern is detected at RPOS and RNEG. The PRBS pattern can be framed, un-framed, or in a specific time slot.
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IMR1 (18 Hex): INTERRUPT MASK REGISTER 1 SYMBOL RSA1 BIT 7 NAME AND DESCRIPTION Receive Signaling All Ones. 0=interrupt masked 1=interrupt enabled Receive Distant MF Alarm. 0=interrupt masked 1=interrupt enabled Receive Signaling All Zeros. 0=interrupt masked 1=interrupt enabled Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All Ones. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled
RDMA
6
RSA0
5
RSLIP
4
RUA1
3
RRA
2
RCL
1
RLOS
0
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DS21Q50
IMR2 (19 Hex): INTERRUPT MASK REGISTER 2 SYMBOL RMF BIT 7 NAME AND DESCRIPTION Receive CAS Multiframe. 0=interrupt masked 1=interrupt enabled Receive Align Frame. 0=interrupt masked 1=interrupt enabled Transmit Multiframe. 0=interrupt masked 1=interrupt enabled One Second Timer. 0=interrupt masked 1=interrupt enabled Transmit Align Frame. 0=interrupt masked 1=interrupt enabled Loss Of Transmit Clock. 0=interrupt masked 1=interrupt enabled Receive CRC4 Multiframe. 0=interrupt masked 1=interrupt enabled Pseudo Random Bit Sequence Detect. 0=interrupt masked 1=interrupt enabled
RAF
6
TMF
5
SEC
4
TAF
3
LOTC
2
RCMF
1
PRBSD
0
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DS21Q50
8. ERROR COUNT REGISTERS There are a set of four counters in each transceiver of the DS21Q50 that record bipolar or code violations, errors in the CRC4 SMF code words, E bits as reported by the far end, and word errors in the FAS. The EBit counter is re-configured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four counters are automatically updated on either one second boundaries (CCR2.7=0) or every 62.5 ms (CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt from the one second timer to determine when to read these registers. The user has a full second (or 62.5 ms) to read the counters before the data is lost. All four counters will saturate at their respective maximum counts and they will not rollover.
8.1 BPV or Code Violation Counter Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of a 16-bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0, then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same polarity. In this mode, if the HDB3 mode is set for the receiver via CCR1.2, then HDB3 code words are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10** -2 before the VCR would saturate.
VCR1 (00 Hex), VCR2 (01 Hex): BIPOLAR VIOLATION COUNT REGISTER (MSB) V15 V7 SYMBOL V15 V0 (LSB) V8 V0
V14 V6
V13 V5 BIT VCR1.7 VCR2.0
V12 V4
V11 V3
V10 V2
V9 V1
VCR1 VCR2
NAME AND DESCRIPTION MSB of the 16-bit code violation count LSB of the 16-bit code violation count
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8.2 CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. CRCCR1 and CRCCR2 have an alternate function.
CRCCR1 (02 Hex), CRCCR2 (03 Hex): CRC4 COUNT REGISTERS (MSB) CRC15 CRC7 SYMBOL CRC9 CRC0 (LSB) CRC8 CRC0
CRC14 CRC6
CRC13 CRC5 BIT
CRC12 CRC4
CRC11 CRC/3
CRC10 CRC2
CRC9 CRC1
CRCCR1 CRCCR2
NAME AND DESCRIPTION MSB of the 10-Bit CRC4 error count LSB of the 10-Bit CRC4 error count
CRCCR1.1 CRCCR2.0
8.3 E-Bit / PRBS Bit Error Counter E-bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These error count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. Alternately, this counter will count bit errors in the received PRBS pattern when the receive PRBS function is enabled. In this mode, the counter is active when the receive PRBS detector can synchronize to the PRBS pattern. This pattern may be framed, unframed or in any time slot. See section 10 for more details.
EBCR1 (04 Hex), EBCR2 (05 Hex): E-BIT COUNT REGISTERS (MSB) EB15 EB7 SYMBOL EB9 EB0 (LSB) EB8 EB0
EB14 EB6
EB13 EB5 BIT EBCR1.1 EBCR2.0
EB12 EB4
EB11 EB3
EB10 EB2
EB9 EB1
EBCR1 EBCR2
NAME AND DESCRIPTION MSB of the 10-Bit E-Bit Error Count LSB of the 10-Bit E-Bit Error Count
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DS21Q50
8.4 FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one second period is 4000, this counter cannot saturate.
FASCR1 (06 Hex), FASCR2 (07 Hex): FAS ERROR COUNT REGISTERS (MSB) FAS15 FAS7 SYMBOL FAS11 FAS0 (LSB) FAS8 FAS0
FAS14 FAS6
FAS13 FAS5 BIT
FAS12 FAS4
FAS11 FAS3
FAS10 FAS2
FAS9 FAS1
FASCR1 FASCR2
NAME AND DESCRIPTION MSB of the 12-Bit FAS Error Count LSB of the 12-Bit FAS Error Count
FASCR1.7 FASCR2.2
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DS21Q50
9. DS0 MONITORING FUNCTION Each framer in the DS21Q50 has the ability to monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0 to RCM4 bits in the CCR4 register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into CCR4 and CCR5: TCM4 = 0 TCM3 = 0 TCM2 = 1 TCM1 = 0 TCM0 = 1 RCM4 = 0 RCM3 = 1 RCM2 = 1 RCM1 = 1 RCM0 = 0
CCR3 (14 Hex): COMMON CONTROL REGISTER 3 [Repeated here from section 6 for convenience] SYMBOL RLB LLB LIAIS TCM4 BIT 7 6 5 4 NAME AND DESCRIPTION Remote Loopback. Local Loopback. Line Interface AIS Generation Enable. Transmit Channel Monitor Bit 4. MSB of a channel decode that determines which transmit channel data will appear in the TDS0M register. See Section 9 or details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode.
TCM3 TCM2 TCM1 TCM0
3 2 1 0
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TDS0M (22 Hex): TRANSMIT DS0 MONITOR REGISTER SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION
DS21Q50
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6. Transmit DS0 Channel Bit 7. Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be transmitted).
CCR4 (15 Hex): COMMON CONTROL REGISTER 4 [Repeated here from section 6 for convenience] SYMBOL LIRST RESALGN RESR RCM4 BIT 7 6 5 4 NAME AND DESCRIPTION Line Interface Reset. Receive Elastic Store Align. Receive Elastic Store Reset. Receive Channel Monitor Bit 4. MSB of a channel decode that deter-mines which receive channel data will appear in the RDS0M register. See Section 9 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode.
RCM3 RCM2 RCM1 RCM0
3 2 1 0
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RDS0M (2A Hex): RECEIVE DS0 MONITOR REGISTER SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION
DS21Q50
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7. Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit received).
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DS21Q50
10. PRBS GENERATION & DETECTION The DS21Q50 can transmit and receive the 215-1 PRBS pattern. This PRBS pattern complies with ITU-T O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0), or in any single time slot. Register CCR5 contains the control bits for configuring the transmit and receives PRBS functions. Refer to Table 10-1 and Table 10-2 for selecting the transmit and receive modes of operation. In transmit and receive mode 1 operation, the Transmit Channel Monitor and Receive Channel Monitor select bits of registers CCR3 and CCR4 have an alternate use. When this mode is selected, these bits will determine which time slot will transmit and/or receive the PRBS pattern. SR2.0 will indicate when the receiver has synchronized to the PRBS pattern. The PRBS synchronizer will remain in sync until it experiences 6 bit errors or more within a 64 bit span. Choosing any receive mode, other than NORMAL, will cause the 16 bit E-Bit error counter, EBCR1 and EBCR2, to be re-configured for counting PRBS errors. User definable outputs OUTA or OUTB may be configured to output a pulse for every bit error received. See section 17 and Table 17-1 for details. This signal can be used with external circuitry to keep track of bit error rates during PRBS testing. Once synchronized, any bit errors received will cause a positive going pulse, synchronous with RCLK. Table 10-1 TRANSMIT PRBS MODE SELECT TPRBS1 (CCR5.3) 0 0 TPBRS0 (CCR5.2) 0 1 MODE Mode 0: Normal (PRBS disabled) Mode 1: PRBS in TSx. PRBS pattern is transmitted in a single time slot (TS). In this mode the Transmit Channel Monitor select bits in register CCR3 are used to select a time slot in which to transmit the PRBS pattern. Mode 2: PRBS in all but TS0. PRBS pattern is transmitted in time slots 1 through 31 Mode 3: PRBS unframed. PRBS pattern is transmitted in all time slots
1 1
0 1
Table 10-2 RECEIVE PRBS MODE SELECT RPRBS1 (CCR5.1) 0 0 RPBRS0 (CCR5.0) 0 1 MODE Mode 0: Normal (PRBS disabled) Mode 1: PRBS in TSx. PRBS pattern is received in a single time slot (TS). In this mode the Receive Channel Monitor select bits in register CCR4 are used to select a time slot in which to receive the PRBS pattern. Mode 2: PRBS in all but TS0. PRBS pattern is received in time slots 1 through 31 Mode 3: PRBS unframed. PRBS pattern is received in all time slots
1 1
0 1
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DS21Q50
11. SYSTEM CLOCK INTERFACE A single System Clock Interface (SCI) is common to all four transceivers on the DS21Q50. The SCI is designed to allow any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q50s are used to build an N port system, the SCI will allow any one of the N ports to be the master. The selected reference is then distributed to the other DS21Q50s via the REFCLK pin. The REFCLK pin acts as an output on the DS21Q50, which has been selected to provide the reference clock from one of its four receivers. On DS21Q50s not selected to source the reference clock, this pin becomes an input. The reference clock is also passed to the clock synthesizer PLL to generate a 2.048MHz, 4.096MHz, 8.192MHz or 16.384MHz clock. This clock can then be used with the IBO function in order to merge up to 8 E1 lines on to a single high-speed PCM bus. In the event that the master E1 port fails (enters a Receive Carrier Loss condition) that port will automatically switch to the clock present on the MCLK pin. Therefore, MCLK acts as the backup source of master clock. The host can then find and select a functioning E1 port as the master. Because the selected port' clock is passed to the other s DS21Q50s in a multiple device configuration, one DS21Q50' synthesizer can always be the source of the s high-speed clock. This allows smooth transitions when clock source switching occurs. The System Clock Interface Control register exists in transceiver #1 only. (TS0, TS1 = 0)
SCICR (1D Hex): SYSTEM CLOCK INTERFACE CONTROL REGISTER SYMBOL BUCS BIT 7 6 Back-Up Clock Select. Selects which clock source to switch to automatically during a Loss Of Transmit Clock event. 0 = During a LOTC event, switch to MCLK. 1 = During a LOTC event, switch to system reference clock Synthesizer Output Enable. 0 = 2/4/8/16MCK pin in high z mode 1 = 2/4/8/16MCK pin active Clock Synthesizer Select Bit 1. See Clock Synthesizer Output table below Clock Synthesizer Select Bit 0. See Clock Synthesizer Output table below System Clock Select Bit 2. See System Clock Select table below System Clock Select Bit 1. See System Clock Select table below System Clock Select Bit 0. See System Clock Select table below NAME AND DESCRIPTION
SOE
5
CSS1 CSS0 SCS2 SCS1 SCS0
4 3 2 1 0
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DS21Q50
Table 11-1 MASTER PORT SELECTION SCS2 0 0 0 0 1 1 1 1 SCS1 0 0 1 1 0 0 1 1 SCS0 0 1 0 1 0 1 0 1 Port Selected As Master None (Master Port may be derived from another DS21Q50 in the system) Transceiver #1 Transceiver #2 Transceiver #3 Transceiver #4 Reserved for future use Reserved for future use Reserved for future use
Table 11-2 SYNTHESIZER OUTPUT SELECT CSS1 0 0 1 1 CSS0 0 1 0 1 Synthesizer Output Frequency 2.048MHz 4.096MHz 8.192MHz 16.384MHz
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DS21Q50
12. TRANSMIT CLOCK SOURCE Depending on the operating mode of the DS21Q50, the Transmit Clock can be derived from different sources. In a basic configuration, where the IBO function is disabled, the transmit clock is normally sourced from the TCLK pin. In this mode a 2.048MHz clock with +/- 50ppm accuracy is applied to the TCLK pin. If the signal at TCLK is lost, the DS21Q50 will automatically switch to either the system reference clock present on the REFCLK pin, or to the recovered clock off the same port depending on which source the host at assigned as the backup clock. At the same time the host can be notified of the loss of transmit clock via an interrupt. The host may at any time force a switch over to one of the two backup clock sources regardless of the state of the TCLK pin. When the IBO function is enabled, the transmit clock must be synchronous to the system clock since slips are not allowed in the transmit direction. In this mode, the TCLK pin is ignored and a transmit clock is automatically provided by the IBO circuit by dividing the clock present on the SYSCLK pin by 2, 4, or 8. In this configuration, if the signal present on the SYSCLK pin is lost, the DS21Q50 will automatically switch to either the system reference clock or to the recovered clock off the same port depending on which source the host at assigned as the backup clock. The host may at any time force a switch over to one of the two backup clock sources regardless of the state of the SYSCLK pin.
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DS21Q50
13. IDLE CODE INSERTION The Transmit Idle Registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This allows the same 8-bit code to be placed into any of the 32 E1 channels. Each of the bit positions in the Transmit Idle Registers represents a DS0 channel in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle Code contained in the Transmit Idle Definition Register (TIDR).
TIR1 (24 Hex), TIR2 (25 Hex), TIR3 (26 Hex), TIR4 (27 Hex): TRANSMIT IDLE REGISTERS (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TIR1 (24) TIR2 (25) TIR3 (26) TIR4 (27)
SYMBOLS CH1 - CH32
BIT TIR1.0 - 4.7
NAME AND DESCRIPTION Transmit Idle Code Insertion Control Bits. 0 = do not insert the Idle Code in the TIDR into this channel 1 = insert the Idle Code in the TIDR into this channel
TIDR (23 Hex): TRANSMIT IDLE DEFINITION REGISTER SYMBOL TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
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DS21Q50
14. PER-CHANNEL LOOP BACK The DS21Q50 has per-channel loop back capability that can operate in one of two modes, Remote PerChannel Loop Back or Local Per-Channel Loop Back. PCLB1/2/3/4 are used for both modes to determine which channels will be looped back. In Remote Per-Channel Loop Back mode, PCLB1/2/3/4 will determine which channels (if any) in the transmit direction should be replaced with the data from the receiver or in other words, off of the E1 line. In Local Per-Channel Loop Back mode, PCLB1/2/3/4 will determine which channels (if any) in the receive direction should be replaced with the data from the transmit. If either mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. There are no restrictions on which channels can be looped back or on how many channels can be looped back.
PCLB1 (2B Hex), PCLB2 (2C Hex), PCLB3 (2D Hex), PCLB4 (2E Hex): PER-CHANNEL LOOPBACK REGISTERS (MSB) CH8 CH16 CH24 CH32 (LSB) CH1 CH9 CH17 CH25
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
PCLB1 (2B) PCLB2 (2C) PCLB3 (2D) PCLB4 (2E)
SYMBOLS CH1 - 32
BIT PCLB1.0 - 4.7
NAME AND DESCRIPTION Per-Channel Loopback Control Bits. 0 = do not loopback this channel 1 = loopback this channel
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DS21Q50
15. ELASTIC STORE OPERATION The DS21Q50 contains a two-frame (512 bits) elastic store, for the receive direction. The elastic store is used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 2.048MHz for normal operation or 4.096MHz, 8.192MHz, or 16.384MHz when using the Interleave Bus Option. The elastic store contains full controlled slip capability. If the receive elastic store is enabled (RCR.4=1), then the user must provide a 2.048MHz clock to the SYSCLK pin. If the IBO function is enabled then a 4.096MHz, 8.192MHz or 16.384MHz clock must be provided at the SYSCLK pin. The user has the option of either providing a frame/multiframe sync at the RSYNC pin (RCR.5=1) or having the RSYNC pin provide a pulse on frame/multiframe boundaries (RCR.5=0). If the user wishes to obtain pulses at the frame boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then RCR.6 must be set to one. If the elastic store is enabled, then either CAS (RCR.7=0) or CRC4 (RCR.7=1) multiframe boundaries will be indicated via the RSYNC output. See Section 21.1 for timing details. If the 512-bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data (256-bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a one.
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16. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION On the receiver, the RAF and RNAF registers will always report the data as it received in the Additional and International bit locations. The RAF and RNAF registers are updated with the setting of the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost. On the transmitter, data is sampled from the TAF and TNAF registers with the setting of the Transmit Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E-bit insertion enabled. Data in the Sa bit position will be overwritten if any of the TCR.3 to TCR.7 bits are set to one. Please see the register descriptions for TCR for more details.
RAF (28 Hex): RECEIVE ALIGN FRAME REGISTER SYMBOL Si 0 0 1 1 0 1 1 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit. Frame Alignment Signal Bit.
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RNAF (29 Hex): RECEIVE NON-ALIGN FRAME REGISTER SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
DS21Q50
TAF (20 Hex): TRANSMIT ALIGN FRAME REGISTER [Must be programmed with the seven bit FAS word; the DS21Q50 does not automatically set these bits] SYMBOL Si 0 0 1 1 0 1 1 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION International Bit. Frame Alignment Signal Bit. Set this bit = 0 Frame Alignment Signal Bit. Set this bit = 0 Frame Alignment Signal Bit. Set this bit = 1. Frame Alignment Signal Bit. Set this bit = 1. Frame Alignment Signal Bit. Set this bit = 0 Frame Alignment Signal Bit. Set this bit = 1. Frame Alignment Signal Bit. Set this bit = 1.
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TNAF (21 Hex): TRANSMIT NON-ALIGN FRAME REGISTER [Bit 2 must be programmed to one; the DS21Q50 does not automatically set this bit] SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Set this bit = 1 Remote Alarm (used to transmit the alarm). Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
DS21Q50
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DS21Q50
17. USER CONFIGURABLE OUTPUTS There are two user configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, logic 0 and 1 levels to control external circuitry or access transmit data between the framer and transmit line interface unit. OUTA and OUTB can be active low or active high when operating as clock and alarm outputs. OUTA is active high if OUTAC.4 =1, and active low if OUTAC.3 = 0. OUTB is active high if OUTBC.4 =1, and active low if OUTBC.4 = 0. See Table 17-1. For controlling external circuitry, mode 0000 is selected. In this configuration, the OUTA pin will follow OUTAC.4 and the OUTB pin will follow OUTBC.4. The OUTAC register also contains a control bit for CMI operation. Please see section 18 for details on CMI operation.
OUTAC (1A Hex): OUTA CONTROL REGISTER SYMBOL BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION
CMII CMIE OA4 OA3 OA2 OA1 OA0
CMI Invert. CMI Enable. See section 18 for details OUTA control bit 4. Inverts OUTA output OUTA control bit 3. See Table 17-1 for details. OUTA control bit 2. See Table 17-1 for details OUTA control bit 1. See Table 17-1 for details OUTA control bit 0. See Table 17-1 for details
OUTBC (1B Hex): OUTB CONTROL REGISTER SYMBOL OB7 OB4 OB3 OB2 OB1 OB0 BIT 7 6 5 4 3 2 1 0 NAME AND DESCRIPTION
OUTB control bit 4. OUTB control bit 3. OUTB control bit 2. OUTB control bit 1. OUTB control bit 0.
Inverts OUTB output See Table 17-1 for details See Table 17-1 for details See Table 17-1 for details See Table 17-1 for details
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DS21Q50
Table 17-1 OUTA AND OUTB FUNCTION SELECT OA3/ OB3 0 OA2/ OB2 0 OA1/ OB1 0 OA0/ OB0 0 FUNCTION External Hardware Control Bit. In this mode OUTA and OUTB can be used as simple control pins for external circuitry. Use OA4 and OB4 to toggle OUTA and OUTB. RCLK. Receive Recovered Clock Receive Loss Of Sync Indicator. Real-time hardware version of SR1.0. See Table 7-1. Receive Loss Of Carrier Indicator. Real-time hardware version of SR1.1. See Table 7-1. Receive Remote Alarm Indicator. Real-time hardware version of SR1.2. See Table 7-1. Receive Unframed All Ones Indicator. Real-time hardware version of SR1.3. See Table 7-1. Receive Slip Occurrence Indicator. One clock wide pulse for every slip of the receive elastic store. Hardware version of SR1.4. Receive CRC Error Indicator. One clock wide pulse for every multiframe that contains a CRC error. Output forced to 0 during loss of sync. Loss Of Transmit Clock Indicator. Real-time hardware version SR2.2. See Table 7-1. RFSYNC. Recovered frame sync pulse. PRBS Bit Error. A one clock wide pulse for every bit error in the received PBRS pattern. TDATA / RDATA. OUTB will output an NRZ version of the transmit data stream (TDATA) prior to the transmit line interface. OUTA will output the received serial data stream (RDATA) prior to the Elastic Store. Receive CRC4 Multiframe Sync. Recovered CRC4 MF sync pulse. Receive CAS Multiframe Sync. Recovered CAS MF sync pulse. Transmit Current Limit. Real-time indicator that the TTIP and TRING outputs have reached their 50ma current limit. TPOS / TNEG Output. This mode outputs the AMI/HDB3 encoded transmit data. OUTA will output TNEG data. OUTB will output TPOS data.
0 0 0 0 0 0 0
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 1 1
0 0 0 0
0 0 1 1
0 1 0 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
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DS21Q50
18. LINE INTERFACE UNIT The line interface unit in the DS21Q50 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter attenuator. The Line Interface Control Register (LICR) which is described below controls each of these three sections.
LICR (17 Hex): LINE INTERFACE CONTROL REGISTER SYMBOL L2 L1 L0 EGL BIT 7 6 5 4 NAME AND DESCRIPTION Line Build Out Select Bit 2. Sets the transmitter build out. See Table 18-1. Line Build Out Select Bit 1. Sets the transmitter build out. See Table 18-1. Line Build Out Select Bit 0. Sets the transmitter build out. See Table 18-1. Receive Equalizer Gain Limit. 0 = -12 dB 1 = -43 dB Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place the jitter attenuator on the transmit side Jitter Attenuator Buffer Depth Select. 0 = 128 bits 1 = 32 bits (use for delay sensitive applications) Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled Transmit Power Down. 0 = normal transmitter operation 1 = powers down the transmitter and 3-states the TTIP and TRING pins
JAS
3
JABDS
2
DJA
1
TPD
0
18.1 Receive Clock And Data Recovery The DS21Q50 contains a digital clock recovery system. See Figure 3-1 and Figure 18-1 for more details. The device couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See Table 18-2 for transformer details. The 2.048 MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over-sampler which is used to recover the clock and data. This oversampling technique offers outstanding jitter tolerance (see Figure 18-4). Normally, RCLK is the recovered clock from the E1 AMI/HDB3 waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive Carrier Loss (RCL) condition will occur and the RCLK will be sourced from the clock applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, RCLK can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC Timing Characteristics in Section 23.3 for more details.
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DS21Q50
18.1.1 Termination The DS21Q50 is designed to be fully software-selectable for 75 ohm and 120 ohm termination without the need to change any external resistors. The user can configure the DS21Q50 for 75 or 120 ohm receive termination by setting the IRTSEL (CCR5.4) bit. When using the internal termination feature, the external termination resistance should be120 ohms (typically two 60 ohm resistors). Setting IRTSEL = 1 will cause the DS21Q50 to internally apply parallel resistance to the external resistors in order to adjust the termination to 75 ohms. See Figure 18-2 for details.
18.2 Transmit Waveshaping And Line Driving The DS21Q50 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications. See Figure 18-3. The user will select which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR). The DS21Q50 can set up in a number of various configurations depending on the application. See Table 18-1. Table 18-1 LINE BUILD OUT SELECT IN LICR L2 L1 L0 APPLICATION TRANSFORMER RETURN LOSS* NM NM NM NM 21dB 21dB RT** 0 ohms 0 ohms 2.5 ohms 2.5 ohms 6.2 ohms 11.6 ohms
0 0 0 75 ohm normal 1:2 step-up 0 0 1 120 ohm normal 1:2 step-up 0 1 0 75 ohm w/ protection resistors 1:2 step-up 0 1 1 120 ohm w/ protection resistors 1:2 step-up 1 0 0 75 ohm w/ high return loss 1:2 step-up 1 0 1 120 ohm w/ high return loss 1:2 step-up * NM = Not Meaningful (Return Loss value too low for significance) ** See separate application note for details on E1 line interface design
Due to the nature of the design of the transmitter in the DS21Q50, very little jitter (less then 0.005 UIpp broadband from 10 Hz to 100 kHz) is added to the jitter present on TCLK (or source used for transmit clock). Also, the waveform created is independent of the duty cycle of TCLK. The transmitter in the device couples to the E1 transmit shielded twisted pair or COAX via a 1:2 step up transformer as shown in Figure 18-1. In order for the devices to create the proper waveforms, the transformer used must meet the specifications listed in Table 18-2. The line driver in the device contains a current limiter that will prevent more than 50 mA (rms) from being sourced in a 1 ohm load. Table 18-2 TRANSFORMER SPECIFICATIONS SPECIFICATION Turns Ratio Primary Inductance Leakage Inductance Intertwining Capacitance DC Resistance RECOMMENDED VALUE 1:1(receive) and1:2(transmit)? ? 3% 600H minimum 1.0H maximum 40 pF maximum 1.2 Ohms maximum
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Figure 18-1 EXTERNAL ANALOG CONNECTIONS (BASIC CONFIGURATION)
DS21Q50
0.47uF (nonpolarized) E1 Transmit Line 2:1 1:1 E1 Receive Line Rr 0.1uF Rr
1/4 DS21Q50 +3.3V 0.1uF TTIP TRING DVDD DVSS RVDD RVSS RTIP RRING TVDD TVSS MCLK 0.01uF 0.1uF
0.1uF 2.048 MHz
Notes: 1. All resistor values are +/- 1%.
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DS21Q50
Figure 18-2 EXTERNAL ANALOG CONNECTIONS (PROTECTED INTERFACE)
+VDD D1 D2 +VDD
Fuse
2:1
S
TTIP1 Transmit Line
Fuse
0.47uF (nonpolarized)
C1
DVDD DVSS RVDD RVSS TVDD TVSS
0.1uF
TRING1
D4
0.01uF 0.1uF
68uF
D3
0.1uF
+VDD
1/4 DS21Q50
D5 Fuse D6
1:1
RTIP1
S C2
Receive Line
Fuse 60
RRING1
D8
MCLK
2.048MHz
60 D7
0.1uF
Notes: 2. All resistor values are +/- 1%. 3. C1 = C2 = 0.1uF. 4. S is a 6V transient suppresser. 5. D1 to D8 are Schottky diodes. 6. The fuses are optional to prevent AC power line crosses from compromising the transformers. 7. The 68F is used to keep the local power plane potential within tolerance during a surge.
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DS21Q50
Figure 18-3 TRANSMIT WAVEFORM TEMPLATE
1.2 1.1 1.0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 Template
TIME (ns)
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DS21Q50
18.3 Jitter Attenuators The DS21Q50 contains an onboard clock and data jitter attenuator for each transceiver and a single, undedicated "clock only" jitter attenuator. This undedicated jitter attenuator is shown in the block diagram of Figure 3-1 as the Alternate Jitter Atteunator.
18.3.1 Clock And Data Jitter Attenuators The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer depths of either 32 or 128 bits via the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuators are shown in Figure 18-5. The jitter attenuators can be placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR. In order for the jitter attenuator to operate properly, a 2.048 MHz clock (? 50 ppm) must be applied at the MCLK pin. Onboard circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLKI pin to create a smooth jitter free clock which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIpp (buffer depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS21Q50 will divide the internal nominal 32.768 MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register (RIR.5).
18.3.2 Undedicated Clock Jitter Attenuator The undedicated jitter attenuator is useful for preparing a user supplied clock for use as a transmission clock (TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL or other synthesizers may contain too much jitter to be appropriate for transmission. Network requirements limit the amount of jitter that may be transmitted onto the network. The undedicated attenuator may be hardware configured by the user.
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Figure 18-4 JITTER TOLERANCE
DS21Q50
1K
UNIT INTERVALS (UIpp)
100
40
DS21Q50 Tolerance
10
1.5
1
Minimum Tolerance Level as per ITU G.823
20 2.4K 18K
0.2
0.1 1 10
100 1K FREQUENCY (Hz)
10K
100K
Figure 18-5 JITTER ATTENUATION
0dB
JITTER ATTENUATION (dB)
ITU G.7XX Prohibited Area
ion at nu tte rA te Jit
-20dB
ETS 300 011 & TBR12 Prohibited Area
e rv Cu
-40dB
-60dB
40
1
10
100 1K FREQUENCY (Hz)
10K
100K
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DS21Q50
19. CMI (Code Mark Inversion) The DS21Q50 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B coded signal. Ones are alternately encoded as a logical one or zero level for the full duration of the clock period. Zeros are encode as a 0 to 1 transition at the middle of the clock period. Figure 19-1 shows an example data pattern and its CMI result. The control bit for enabling CMI is in the OUTAC register as shown below. OUTAC (1A Hex): OUTA CONTROL REGISTER (Partially reproduced here for clarity) SYMBOL TRCMIE BIT 7 NAME AND DESCRIPTION Transmit and Receive CMI Enable. See section 18 for details 0 = Transmit and Receive line interface operates in normal AMI/HDB3 mode 1 = Transmit and Receive line interface operate in CMI mode. TTIP is CMI output and RTIP is CMI input. In this mode of operation TRING and RRING are no-connects.
OA4 OA3 OA2 OA1 OA0
6 5 4 3 2 1 0
Figure 19-1 CMI CODING
CLOCK DATA CMI
1
1
0
1
0
0
1
Transmit and Receive CMI is enabled via OUTAC.7. When this register bit is set, the TTIP pin will output CMI coded data at normal TTL type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the user may also use HDB3 coding.
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DS21Q50
When this register bit is set, the RTIP pin will become a unipolar CMI input. The CMI signal will be processed to extract and align the clock with data. The BiPolar code violation counter will count CVs (Code Violations) in the CMI signal. CVs are defined as consecutive ones of the same polarity as shown in Figure 19-2. If HDB3 pre-coding is enabled then the CVs generated by HDB3 will not be counted as errors.
Figure 19-2 EXAMPLE OF CMI CODE VIOLATION (CV) CLOCK DATA CMI
1
1
0
1
0
0
1
CODE VIOLATION
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DS21Q50
20. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data buses to be multiplexed into higher speed data and buses eliminating external hardware, saving board space and cost. The DS21Q50 uses a channel interleave method. See Figure 21-4 and Figure 21-7 for details of the channel interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.096 MHz bus speed allows two PCM data streams to share a common bus. The 8.192 MHz bus speed allows four PCM data streams to share a common bus. The 16.384 MHz bus speed allows 8 PCM data streams to share a common bus. See Figure 20-1 for an example of 4 transceivers sharing a common 8.192MHz PCM bus. The receive elastic stores of each transceiver must be enabled. Via the IBO register the user can configure each transceiver for a specific bus speed and position. For all IBO bus configurations each transceiver is assigned an exclusive position in the high speed PCM bus.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = 1B Hex) (MSB) SYMBOL IBOTCS (LSB) DA0
IBOTCS BIT 7 6
SCS1
SCS0
IBOEN
DA2
DA1
NAME AND DESCRIPTION Not Assigned. Should be set to 0. IBO Transmit Clock Source. 0 = TCLK pin will be source of transmit clock 1 = Transmit clock will internally derived from the clock at the SYSCLK pin System Clock Select bit 1 See Table 20-2
SCS1
5
SCS0
4
System Clock Select bit 0 See Table 20-2
IBOEN
3
DA2 DA1 DA0
2 1 0
Interleave Bus Operation Enable 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Device Assignment bit 3 See Table 20-1 Device Assignment bit 2 See Table 20-1 Device Assignment bit 1 See Table 20-1
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DS21Q50
Table 20-1 IBO DEVICE ASSIGNMENT DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Function 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus
Table 20-2 IBO SYSTEM CLOCK SELECT SCS1 0 0 1 1 SCS0 0 1 0 1 Function 2.048MHz, Single device on bus 4.096MHz, Two devices on bus 8.192MHz, Four devices on bus 16.384MHz, Eight devices on bus
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DS21Q50
Figure 20-1 IBO CONFIGURATION USING 2 DS21Q50 QUAD TRANSCEIVERS (8 E1 Lines)
XFMR XFMR XFMR XFMR XFMR XFMR XFMR XFMR PCM IN 16.384MHz Interleaved PCM OUT PCM BUS
E1 #1
TTIP1/TRING1 RTIP1/RRING1
TSER1 RSER1 SYSCLK1 RSYNC1 TSER2 RSER2 SYSCLK2 RSYNC2 TSER3 RSER3 SYSCLK3 RSYNC3 TSER4 RSER4 SYSCLK4 RSYNC4
E1 #2
TTIP2/TRING2 RTIP2/RRING2
DS21Q50
E1 #3
TTIP3/TRING3 RTIP3/RRING3
E1 #4
TTIP4/TRING4 RTIP4/RRING4 REFCLK 4/8/16MCK
E1 #5
XFMR XFMR XFMR XFMR XFMR XFMR XFMR XFMR
TTIP1/TRING1 RTIP1/RRING1
REFCLK
4/8/16MCK
TSER1 RSER1 SYSCLK1 RSYNC1 TSER2 RSER2 SYSCLK2 RSYNC2 TSER3 RSER3 SYSCLK3 RSYNC3 TSER4 RSER4 SYSCLK4 RSYNC4
16.384 MHz CLOCK DERIVED FROM ONE OF THE EIGHT E1 LINES
E1 #6
TTIP2/TRING2 RTIP2/RRING2
DS21Q50
E1 #7
TTIP3/TRING3 RTIP3/RRING3
E1 #8
TTIP4/TRING4 RTIP4/RRING4
Note: See Section 18 for details on Line Interface circuit.
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DS21Q50
21. FUNCTIONAL TIMING DIAGRAMS 21.1 Receive Figure 21-1 RECEIVE FRAME AND MULTIFRAME TIMING
FRAME# RSYNC 1 RSYNC
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Notes: 1. RSYNC in frame/output mode (RCR.6 = 0) 2. RSYNC in multiframe/output mode (RCR.6 = 1) 3. This diagram assumes the CAS MF begins in the RAF frame
Figure 21-2 RECEIVE BOUNDARY TIMING (with elastic store disabled)
RCLK
CHANNEL 32 CHANNEL 1
LSB
CHANNEL 2
RSER RSYNC
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
Figure 21-3 RECEIVE BOUNDARY TIMING (with elastic store enabled)
SYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB MSB
CHANNEL 1
RSER RSYNC1
RSYNC
2
Notes: 1. RSYNC is in the output mode (RCR.5 = 0) 2. RSYNC is in the input mode (RCR.5 = 1)
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Figure 21-4 RECEIVE INTERLEAVE BUS OPERATION RSYNC RSER
1 FR1 CH32
FR2 CH32 FR3 CH32
DS21Q50
FR0 CH1
FR0 CH1 FR1 CH1
FR1 CH1
FR2 CH1 FR3 CH1
FR0 CH2
FR0 CH2 FR1 CH2
FR1 CH2
FR2 CH2 FR3 CH2
RSER2
BIT DETAIL SYSCLK RSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 1, CHANNEL 1
LSB
RSER
LSB MSB
Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. RSYNC is in the input mode (RCR.5 = 0).
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DS21Q50
21.2 Transmit
Figure 21-5 TRANSMIT FRAME AND MULTIFRAME TIMING
FRAME# TSYNC TSYNC
1
14 15 16 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
9 10
2
Notes: 1. TSYNC in frame mode (TCR.1 = 0) 2. TSYNC in multiframe mode (TCR.1 = 1)
Figure 21-6 TRANSMIT BOUNDARY TIMING TCLK
CHANNEL 1 CHANNEL 2
LSB MSB
TSER TSYNC1 TSYNC2
LSB
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
Notes: 1. TSYNC is in the output mode (TCR.0 = 1) 2. TSYNC is in the input mode (TCR.0 = 0)
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DS21Q50
Figure 21-7 TRANSMIT INTERLEAVE BUS OPERATION TSYNC TSER
1 FR1 CH32 FR0 CH1
FR1 CH1
FR1 CH1
FR2 CH1 FR3 CH1
FR0 CH2
FR0 CH2 FR1 CH2
FR1 CH2
FR2 CH2 FR3 CH2
TSER2
FR2 CH32 FR3 CH32 FR0 CH1
BIT DETAIL SYSCLK TSYNC
3 FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
LSB MSB
FRAMER 1, CHANNEL 1
LSB
TSER
LSB MSB
Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. TSYNC is in the input mode (TCR.0 = 0).
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Figure 21-8 DS21Q50 FRAMER SYNCHRONIZATION FLOWCHART
DS21Q50
Power Up
RLOS=1
FAS Search F S A=1 AS R O =1 LS FAS Sync Criteria Met FASSA = 0 Increment CRC4 Sync Counter; CRC4SA=0 8s m Te im Out CRC4 Multiframe Search (if enabled via CCR1.0) CRC4SA=1 C S M ltiframe Search A u (if enabled via CCR1.3) CASSA = 1
Resync if R R .0 = 0 C1
CRC4 Sync Criteria Met; CRC4SA = 0; Reset CRC4 S ync Counter
Sync Declared RLOS=0
CAS Sync C riteria Met C S A=0 AS
Set FASRC (RIR.1)
FAS Resync C riteria Met
Check for FAS Fram Error ing (depends on RCR1.2)
CRC4 Resync C riteria Met (RIR.2)
Check for >=915 Out of 1000 C C W Errors R 4 ord
If CRC4 is on (CCR1.0 = 1)
CAS Resync Criteria Met; Set CASRC (RIR.0)
Check for CAS MF W Error ord
If C Sis on A (CCR1.3 = 0)
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DS21Q50
Figure 21-9 DS21Q50 TRANSMIT DATA FLOW
TSER
TAF TNAF.5-7
0 Timeslot 0 Pass-Through (TCR.6) 1
1
0 Si Bit Insertion Control (TCR.3) Receive Side CRC4 Error Detector 1 1
CRC4 Multiframe Alignment Word Generation (CCR.4) 0
E-Bit Generation (TCR.5)
Auto Remote Alarm Generation (CCR.4)
TIDR
0 1 Idle Code / Channel Insertion Control via TIR1/2/3/4 0
Code Word Generation 1
CRC4 Enable (CCR.4)
Transmit Unframed All Ones (TCR.4) or Auto AIS (CCR2.5)
AMI or HDB3 Converter CCR.6
To Waveshaping and Line Drivers
KEY:
= Register = Device Pin = Selector
NOTES: 1. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Not Align Frames if the alarm needs to be sent.
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DS21Q50
22. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS21Q50L Operating Temperature for DS21Q50LN Storage Temperature Soldering Temperature
-1.0V to +6.0V 0 to 70 C C -40 to +85 C C -55 to +125 C C 260 for 10 seconds C
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS PARAMETER SYMBOL Logic 1 VIH Logic 0 VIL Supply VDD
MIN 2.0 -0.3 3.135
TYP
3.3
(0 to 70 for DS21Q50L; C C -40 to +85 for DS21Q50LN) C C MAX UNITS NOTES 5.5 V +0.8 V 3.465 V 1
CAPACITANCE PARAMETER Input Capacitance Output Capacitance
SYMBOL CIN COUT
MIN
TYP 5 7
MAX
UNITS pF pF
(tA =25 C) NOTES
DC CHARACTERISTICS PARAMETER Supply Current @ 5V Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) SYMBOL IDD IIL ILO IOH IOL
(0 to 70 VDD = 3.3.0V 5% for DS21Q50L; C C; -40 to +85 VDD = 3.3.0V 5% for DS21Q50LN) C C; MIN TYP MAX UNITS NOTES 75 mA 2 -1.0 +1.0 3 A 1.0 4 A -1.0 mA +4.0 mA
NOTES: 1. Applies to RVDD, TVDD, and DVDD. 1. TCLK = SYSCLK = MCLK = 2.048 MHz; outputs open circuited. 2. 0.0V < VIN < VDD. 3. Applied to INT* when 3-stated.
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DS21Q50
23. AC TIMING PARAMETERS AND DIAGRAMS 23.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS - MULTIPLEXED PARALLEL PORT (MUX = 1) [See Figure 23-1 to Figure 23-3] PARAMETER SYMBOL Cycle Time tCYC Pulse Width, DS low or RD* PWEL high Pulse Width, DS high or PWEH RD* low Input Rise/Fall times tR , tF R/W* Hold Time tRWH R/W* Set Up time before DS tRWS high CS* Set Up time before DS, tCS WR* or RD* active CS* Hold time tCH Read Data Hold time tDHR Write Data Hold time tDHW Muxed Address valid to AS tASL or ALE fall Muxed Address Hold time tAHL Delay time DS, WR* or RD* tASD to AS or ALE rise Pulse Width AS or ALE PWASH high Delay time, AS or ALE to tASED DS, WR* or RD* Output Data Delay time from tDDR DS or RD* Data Set Up time tDSW (0 to 70 VDD = 3.3.0V 5% for DS21Q50L; C C; -40 to +85 VDD = 3.3.0V 5% for DS21Q50LN) C C;
MIN 200 100 100
TYP
MAX
UNITS ns ns ns
NOTES
20 10 50 20 0 10 0 15 10 20 30 10 20 50 80
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
50
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DS21Q50
Figure 23-1 INTEL BUS READ AC TIMING (BTS=0 / MUX = 1)
t CYC ALE t ASD WR*
PWASH t ASED PWEH t CS t CH
t ASD
RD*
PWEL
CS* t ASL AD0-AD7 t AHL t DDR t DHR
Figure 23-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1)
t CYC ALE t ASD RD*
PWASH t ASED PWEH t CS t CH
t ASD
WR*
PWEL
CS* t ASL AD0-AD7 t AHL t DSW t DHW
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DS21Q50
Figure 23-3 MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1)
PWASH AS t ASD DS PWEL t RWS R/W* AD0-AD7 (read) t ASL t AHL CS* AD0-AD7 (write) t ASL t AHL t DSW t DHW t DDR t DHR t CH t ASED t CYC t RWH PWEH
t CS
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Preliminary
DS21Q50
23.2 Non-Multiplexed Bus AC Characteristics AC CHARACTERISTICS - (0 to 70 VDD = 3.3V 5% for DS21Q50L; C C; NON-MULTIPLEXED PARALLEL PORT -40 to +85 VDD = 3.3V 5% for DS21Q50N) C C; (MUX = 0) [See Figure 23-4 to Figure 23-7] PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Set Up Time for A0 to A7, t1 0 ns Valid to CS* Active Set Up Time for CS* Active t2 0 ns to either RD*, WR*, or DS* Active Delay Time from either RD* t3 75 ns or DS* Active to Data Valid Hold Time from either RD*, t4 0 ns WR*, or DS* Inactive to CS* Inactive Hold Time from CS* t5 5 20 ns Inactive to Data Bus 3-state Wait Time from either WR* t6 75 ns or DS* Active to Latch Data Data Set Up Time to either t7 10 ns WR* or DS* Inactive Data Hold Time from either t8 10 ns WR* or DS* Inactive Address Hold from either t9 10 ns WR* or DS* inactive
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Preliminary
Figure 23-4 INTEL BUS READ TIMING (BTS=0 / MUX=0)
DS21Q50
A0 to A7 D0 to D7
Address Valid
Data Valid 5ns min. / 20ns max. t5
WR* t1 CS* 0ns min. RD* t2 t3 75ns max. t4 0ns min. 0ns min.
Figure 23-5 INTEL BUS WRITE TIMING (BTS=0 / MUX=0)
A0 to A7
Address Valid
D0 to D7 t7 RD* t1 0ns min. CS* 0ns min. WR* t2 t6 75ns min. t4 0ns min. 10ns min. t8 10ns min.
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Preliminary
Figure 23-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)
DS21Q50
A0 to A7
Address Valid
D0 to D7
Data Valid 5ns min. / 20ns max. t5
R/W* t1 0ns min. CS* 0ns min. DS* t2 t3 75ns max. t4 0ns min.
Figure 23-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX=0)
A0 to A7
Address Valid
D0 to D7 10ns min. t1 CS* 0ns min. DS* t2 t6 75ns min. t4 0ns min. 0ns min. t7 t8 10ns min.
R/W*
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Preliminary
DS21Q50
23.2.1 Serial Port AC CHARACTERISTICS - SERIAL PORT (BIS1 = 1, BIS0 = 0) [See Figure 23-8] PARAMETER Set Up Time CS* to SCLK Set Up Time SDI to SCLK Hold Time SCLK to SDI SCLK High/Low Time SCLK Rise/Fall Time SCLK to CS* Inactive CS* Inactive Time SCLK to SDO Valid SCLK to SDO Tri-State CS* Inactive to SDO TriState (0 to 70 VDD = 3.3V 5% for DS21Q50L; C C; -40 to +85 VDD = 3.3V 5% for DS21Q50N) C C;
SYMBOL tCSS tSSS tSSH tSLH tSRF tLSC tCM tSSV tSSH tCSH
MIN 50 50 50 200 50 250
TYP
MAX
50
50 100 100
UNITS ns ns ns ns ns ns ns ns ns ns
NOTES
Figure 23-8 SERIAL BUS TIMING (BIS1 = 1, BIS0 = 0)
tCM
CS*
tCSS tSRF tSLH tLSC
SCLK1 SCLK2
tSSS tSSH MSB LSB tSSV MSB tSSH MSB HIGH Z tCSH
SDI SDO
LSB
HIGH Z
LSB
Notes: 1. OCES =1 & ICES = 0. 2. OCES = 0 & ICES = 1.
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Preliminary
DS21Q50
23.3 Receive AC Characteristics AC CHARACTERISTICS - RECEIVER [See Figure 23-9 to Figure 23-10] PARAMETER SYMBOL SYSCLK Period tSP SYSCLK Pulse Width tSH tSL RSYNC Set Up to SYSCLK tSU Falling RSYNC Pulse Width tPW Delay RCLK to RSER Valid tD1 Delay RCLK to RSYNC, tD2 OUTA, OUTB Delay SYSCLK to RSER Valid tD3 Delay SYSCLK to RSYNC, tD4 OUTA, OUTB NOTES: 1. SYSCLK = 2.048 MHz. (0 to 70 VDD = 3.3.0V 5% for DS21Q50L; C C; --40 to +85 VDD = 3.3.0V 5% for DS21Q50LN) C C;
MIN 122 50 50 20 50
TYP 648
MAX
tSH -5
UNITS ns ns ns ns ns ns ns ns ns
NOTES 1
50 50 50 50
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Preliminary
Figure 23-9 RECEIVE AC TIMING (Receive elastic store disabled)
1
DS21Q50
OUTA / OUTB (RCLK)
2
OUTA / OUTB (*RCLK) tD1 RSER
tD2
3
MSB of Channel 1
RSYNC
OUTA / OUTB
4
OUTA / OUTB
5
Notes: 1. OUTA or OUTB configured to output RCLK (non-inverted) 2. OUTA or OUTB configured to output *RCLK (inverted) 3. RSYNC is in the output mode (RCR1.5 = 0) 4. OUTA or OUTB configured to output RFSYNC, CRC4 MF sync, or CAS MF sync (non-inverted) 5. OUTA or OUTB configured to output RFSYNC, CRC4 MF sync, or CAS MF sync (inverted)
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Preliminary
DS21Q50
Figure 23-10 RECEIVE AC TIMING (Receive elastic store enabled)
t SL
tR
tF
t SH
SYSCLK
t D3 t SP
MSB of Channel 1
RSER
1
t D4
RSYNC
OUTA / OUTB 2
t HD t SU
RSYNC
3
Notes: 1. RSYNC is in the output mode (RCR.5 = 0). 2. OUTA or OUTB configured as CRCR MF sync or CAS MF sync. 3. RSYNC is in the output mode (RCR.5 = 1).
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Preliminary
DS21Q50
23.4 Transmit AC Characteristics AC CHARACTERISTICS - TRANSMIT [See Figure 23-11 to Figure 23-12] PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TSYNC Set Up to TCLK tSU TSYNC Pulse Width TSER Set Up to TCLK Falling TSER Hold from TCLK Falling TCLK Rise and Fall Times tPW tSU tHD tR , tF (0 to 70 VDD = 3.3.0V 5% for DS21Q50L; C C; -40 to +85 VDD = 3.3.0V 5% for DS21Q50LN) C C;
MIN 75 75 20 50 20 20
TYP 488
MAX
tCH -5 or tSH -5
UNITS ns ns ns ns ns ns ns ns
NOTES
25
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Preliminary
Figure 23-11 TRANSMIT AC TIMING (IBO Disabled)
t CP tR tF t CL t CH
DS21Q50
TCLK
SU
TSER
t D2
TSYNC1
t SU
t HD
TSYNC 2
t D2
OUTA/OUTB 3
Notes: 1. TSYNC is in the output mode (TCR.0 = 1) 2. TSYNC is in the input mode (TCR.0 = 0) 3. Applies to OUTA and OUTB when configures for TPOS and TNEG outputs.
Figure 23-12 TRANSMIT AC TIMING (IBO Enabled)
t SP tR SYSCLK t SU TSER tF t SL t SH
Notes: 1. TSER is only sampled on the falling edge of SYSCLK when the IBO mode is enabled.
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Preliminary
DS21Q50
24. MECHANICAL DESCRIPTION
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